Personal Capabilities & Other Non-Technical Parameters Can Make a Big Difference in Estimating
Thanks to Galorath’s Sam Sanchez for these insights on non-technical parameters:
When I first started with Galorath, I used to wonder about the usefulness of having parameter inputs like “Developer Experience” or “Development Tools and Practices” within our electronic models. Like many engineers, I didn’t like these types of qualitative inputs, preferring to use more concrete entries like “frequency of board,” “number of ICs/IO” and others. However, as the years have progressed, I am amazed at how critical these qualitative parameters continue to be. Like I heard mentioned in one of my SEER H classes, “There are A teams, B teams and believe it or not even D teams.” More importantly, the impact of these variations can cause dramatic differences in a project’s level of effort.
Common reasons for poor team efficiency could be longevity of the individuals in the given technologies, recent mergers, bad chemistry, poor communication practices and others. It’s important to note that we look at this parameter as an overall assessment of the team.
To help reduce confusion with this input, SEER-IC looks at the following criteria: Accomplishment Metric, Configuration Control, Communications, Adv Skills and Tool Experience. Specific measures within these major sections help users to come up with a reasonable range input. Also, this is definitely one parameter that should have a different entry for “least,”, “likely” or “most.” In other words, there is always some level of risk here.
In SEER-H, swings in Development Experience individually can swing costs by as much as 30%. Development Tools and Practices by as much as 50%. We tend to look at “common” variations. In reality, at times, the variations may be orders of magnitude.
Thank you for reading “Dan on Estimating”, if you would like more information about Galorath’s estimation models, please visit our contact page or call us at +1 310 414-3222.
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Estimating FPGAs
Integrated Circuit estimationis always interesting since traditional metrics for estimating hardware don’t apply. That is why we developed the SEER-IC plug-in for our SEER for Hardware, Electronics Systems. Here is a document on estimating FPGAs that Sam Sanchez is presenting this week.
Thank you for reading “Dan on Estimating”, if you would like more information about Galorath’s estimation models, please visit our contact page or call us at +1 310 414-3222.
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SEER-IC Add-on To SEER-H Gets The Newest Technologies
Galorath has just released a major update to SEER for Hardware, Electronics & Systems. Major enhancements encompass several areas. I am always fascinated by the SEER-IC plug-in that models custom chips (which can be major cost drivers of systems,) as especially the positive feedback we get from organizations building complicated electronic systems.
SEER-IC adds specific features to extend the capability of SEER-H to estimate the development and recurring costs for custom ICs, ASICs and FPGAs. This add-in is tightly integrated with SEER H to facilitate a more effective cost analysis of the circuit card and its critical components.
The Integrated Circuits (IC) option for SEER-H now offers estimation of Mixed Signal and MMIC technologies. This new capability extends SEER IC to cover components designed for RF applications in addition recurring and non-recurring costs of developing a Standard Cell ASIC and FPGA.
Congratulations to the development team and user organizations who assisted with this update.
Thank you for reading “Dan on Estimating”, if you would like more information about Galorath’s estimation models, please visit our contact page or call us at +1 310 414-3222.
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FPGA Growth and Costing
FPGA Growth and Costing
by Sam Sanchez, Technical Director-Electronics
Field Programmable Gate Arrays are continuing to absorb more and more capabilities that used to reside elsewhere on electronic boards. In the past few years, FPGA devices have not only grown in size but also in the amount of embedded cores like processors within their fabric. As these devices have grown in capability, so has the magnitude of effort required to design and test them.  This, in turn, has made it necessary to come up with techniques to cost them separately. These are no longer just expensive components within the board but are now systems in themselves. In order to properly cost these devices, the first thing to wrestle with is how to properly size the designs. In the past, some have used number of gates (similar to the way ASICs are sized), but this just isn’t standardized enough within the FPGA world to allow accurate and consistent sizing across various vendors or technologies. An alternate way to do a first order approximation of the design size is with VHDL although this also has its challenges. Yet another way is through the use of Logic Cells (LC) or Logic Elements (LE).
Although, the definition of a LC/LE varies across different technology nodes, it can be a very good sizing metric. We currently use this sizing method within our SEER-IC model. Another aspect of properly sizing a design is how to give credit for past design effort. Similar to the way that software designers can bring prior efforts into their current design through COTS software, the IC industry can also bring prior effort through Intellectual Property or simply IP logic. Increased use of well designed IP (emphasis on well designed) can reduce the amount of design effort. Of course, testing and verification are still significant tasks that must be done on the entire design (new logic and IP). Being able to settle on a standard sizing process will go a long way in helping to properly capture FPGA costs.
Thank you for reading “Dan on Estimating”, if you would like more information about Galorath’s estimation models, please visit our contact page or call us at +1 310 414-3222.
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SEER for Hardware, Electronics & Systems Can Control Cost Risk of ASICs
I have been pleased with the performance of the detailed IC estimation option in SEER for Hardware Electronics and Systems. Further I am excited that we have a customer providing a webinar in how to apply SEER-IC to costly military communications systems.
Today’s military communication systems are playing an ever expanding critical role in our domestic security as well as the security of our assets abroad. Satellites that are the core of these communication systems are being required to do more complex functions and perform them faster than ever before. To accomplish complex on-orbit tasks, modern space electronics are using advanced micro-electronics in their unit designs. The rapidly changing field of advanced micro-electronics, largely developed by commercial industry, presents a problem for the cost estimator. Common cost estimating techniques using historical data or cost estimating relationships based on historical data are not well suited to address the complexity of today’s electronic devices. . SEER for Hardware-Integrated Circuits Option parametric cost estimating model is being used to develop a cost estimate for ASICs, and what future estimating challenges may be on military space communication satellites.
If you are interested the webinar registration is here.
Thank you for reading “Dan on Estimating”, if you would like more information about Galorath’s estimation models, please visit our contact page or call us at +1 310 414-3222.