FPGA Growth and Costing
FPGA Growth and Costing
by Sam Sanchez, Technical Director-Electronics
Field Programmable Gate Arrays are continuing to absorb more and more capabilities that used to reside elsewhere on electronic boards. In the past few years, FPGA devices have not only grown in size but also in the amount of embedded cores like processors within their fabric. As these devices have grown in capability, so has the magnitude of effort required to design and test them.  This, in turn, has made it necessary to come up with techniques to cost them separately. These are no longer just expensive components within the board but are now systems in themselves. In order to properly cost these devices, the first thing to wrestle with is how to properly size the designs. In the past, some have used number of gates (similar to the way ASICs are sized), but this just isn’t standardized enough within the FPGA world to allow accurate and consistent sizing across various vendors or technologies. An alternate way to do a first order approximation of the design size is with VHDL although this also has its challenges. Yet another way is through the use of Logic Cells (LC) or Logic Elements (LE).
Although, the definition of a LC/LE varies across different technology nodes, it can be a very good sizing metric. We currently use this sizing method within our SEER-IC model. Another aspect of properly sizing a design is how to give credit for past design effort. Similar to the way that software designers can bring prior efforts into their current design through COTS software, the IC industry can also bring prior effort through Intellectual Property or simply IP logic. Increased use of well designed IP (emphasis on well designed) can reduce the amount of design effort. Of course, testing and verification are still significant tasks that must be done on the entire design (new logic and IP). Being able to settle on a standard sizing process will go a long way in helping to properly capture FPGA costs.
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