SEER Quantifies Savings On Military FPGAs (Custom Chips)
Altera used SEER for Hardware Electronics and Systems to quantify the business case for FPGAs The results were published in ECN Asia.
Part of the case study follows:
“In order to illustrate potential design productivity savings in an optimized design flow, a sample FPGA-based design was developed and measured with a third-party design estimation tool. This design example was co-developed with engineers at Galorath, creators of SEER-SW, SEER-H, and SEER-IC software. These tools allow users to enter parametric descriptions of their equipment designs, and to develop cost and schedule estimates for both proposal development and resource planning. The estimates are based on knowledge databases developed by Galorath and various users of the SEER-series software tools.
The military design example shown in Table 1 takes advantage of the 40nm Stratix FPGAs. This cost estimate focuses on the FPGA design only, and includes design, verification, place-and-route, and simulation, but not board design. The SEER-IC estimation tool allows the user to enter lower and upper requirement and parameter limits to measure cost and schedule risk, as well. This design example is assumed to be a very large, multi-channel sensor design. Logic element (LE) cost will likely put it in the Stratix IV class of FPGAs. There is a large number of I/O pins and new design (50 percent). The complexity of both the interfaces (front end) and processing (back end) is relatively high. Current development tools and practices are estimated to be low quality, and the (average) capability of the designers to be nominal. Requirements volatility is assumed to be normal for military programs.
Using a military FPGA design example such as this allows the user to estimate their program cost and schedule, measure progress, and control costs, as shown in Figure 4. In addition, it allows the user to look at the total impact of software productivity as an independent variable in vendor selection.
Using the assumptions described, Table 2 shows the total cost of the military reference design in both hours and dollars, using a placeholder labor hour cost. This will serve as the basis cost for estimating both the impact of software on program cost, as well as potential savings for other programs. Galorath’s SEER-IC tool divides cost into categories of architectural design, detail design, simulation, verification, and implementation, and place-and-route. The total labor effort for this application comes out to 13,800 hours, at a nominal cost of $2.7 million. Because most military programs do not lend themselves to high-volume builds, it is easy to see from this example that the NRE, or design development portion of an FPGA-based design (shown in Figure 5), is becoming one of the largest components, and a cost and schedule driver, of defense electronics. This makes it more important than ever to consider software productivity as a selection factor.
Using this design as an example, the Galorath SEER-IC tool allows the designer to isolate the impact of software on the overall FPGA-based design by leaving all other factors the same, but entering “low quality” and then “very high quality” in the “development tools and practices” input parameter. This yields the following cost swing due to software productivity:
Low-quality development tools and practices $3,199,279
Very high-quality development tools and practices $2,132,852
This equates to a total program development cost difference of $1,066,427, or 33 percent of the development cost. For the purposes of this design example, it will be considered the upper limit of what productivity savings a program can expect to see from adopting a higher productivity tool suite and set of design practices.
The next step in this design example is to determine what characteristics of a military FPGA design will offer the greatest savings from productivity tools, and assessing what potential productivity gains can be made from the Quartus II software.
Military designs are assessed on how interdependent they are with other system FPGAs, and how well the organization can divide functional blocks within a multi-FPGA design in a team-based fashion. Potential design savings is highly dependent on both the degree and methodology of IP re-use and design IP encapsulation within the design organization. Automation of interconnect tasks and data routing can lead to design savings between 10 to 25 percent of this phase of design.
The high degree of unit-level, test and use case-based verification in military designs automatically makes most designs capable of increasing productivity simply through compile time improvements. Characteristics of a design that modulate these savings include requirements volatility, high-level certifications (DO-254), and verification oversight. Total savings in this phase ranges from 10 to 25 percent.
CONCLUSION
Modern military design requirements call for modern FPGA design tools. Design parameters such as compile times have become cost and schedule drivers, and they are beginning to make measurable differences in both the FPGA design and the overall system design budget. When designing a modern military system, it is essential to factor the costs of development into both the program cost baseline, and in your vendor selection criteria.”
Click here to read the entire case study.
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